Recently TSMC has announced that it will go ahead and work on producing a 2nm memory chip by 2025 to be the forerunner in the foundry and memory chip business. This move is to rival Samsung, which also announced in April this year that it will work on 2 nm by 2025.
Before this, Samsung also informed in April that it would start to work on the 3nm chips 3GAE (3 nm-class gate-all-around early) fabrication process, starting in mid-2022.
TSMC is expected to mass-produce the first-gen 3nm chips (N3) for its customers in early 2023 & 2nm by 2025. TSMC informed at TSMC Technology Symposium 2022 this Thursday.
However, before developing the 2nm technology, the TSMC will use advanced 3nm fabrication processes N3P, N3S, and N3X to produce a 3nm chip between 2023 and 2025. 18 This will result in an 18% percent performance increase at the same power while reducing power consumption to 34% if computing is kept consistent.
Intel also announced to reenter manufacturing business with a whopping 80B dollar investment in Arizona and Ohio last year and plans to work on the 1.8nm process starting 2025.
Intel, Samsung, and TSMC are the only competent players in this business for mass production.
Although Samsung and intel are longtime rivals and friends at certain times, Intel has collaborated with TSMC but doesn’t want to share all its prowess in the foundry business with it, while Samsung is trying to outdo TSMC and Intel trying to enter the manufacturing business it seems a likely alliance could form as both can benefit from each other.
Samsung has likely got an advantage this time due to using a more advanced GAAFET (gate-all-around field-effect transistor) architecture compared to TSMC’s FinFET (fin field-effect transistor). Samsung will become the first manufacturer of semiconductors to start using gate-all-around field-effect transistor (GAAFET) architecture with its upcoming 3 nm fabrication process.
Samsung claims the process would enable a 30% performance increase, a 50% power consumption reduction, and up to 80% higher transistor density.
Another development favoring Samsung could be the meeting between Samsung & Intel’s President & CEO.respectively.
After visiting the DAVOS forum in Switzerland, Intel CEO Pat Gelsinger met with Samsung vice-chairman Lee Jae Yong in the Samsung Seocho building in Seoul. Pat also visited several officials of Samsung, including the Co-Ceo and head of Samsung mobile. This meeting took place 10 days after the US president’s visit to S.Korea to Samsung’s electronic plant on May 20.
Targeting to produce at a mass level with wide reach, Samsung has both capability and will to make a market out of this, as we have seen before in many criteria. Also, not forget the recent CXL-based memory development by Samsung and collaborations with IBM, Intel, Montage Technology, AMD & others.
While this business is completely dominated by these three, the Chinese Semiconductor manufacturing Int, Co. also wants to compete. Japanese are working with the US on 2nm to complete by 2025.
The chipmaking tech is extremely difficult to put a complex process requiring precision, clean environments, expensive factory equipment, and time. It takes GlobalFoundries three months on average to engrave and transform mirror-smooth silicon wafers into layered semiconductors, not to mention the lower the nm(nanometer) more difficult it becomes to fit the no. of transistors in a wafer-thin silicon layer.
So, a lower nm transistor means less power is required for it to work. Lower power consumption makes a huge difference overall when you look at all the transistors in a CPU. It makes your processor more power-efficient than a higher nm processor with larger transistors.
Although TSMC has had superiority over Samsung, this time, Samsungs seems to show a promising future.
To learn more about this news, previous developments, and the mentioned technology, refer to the links below.
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