Samsung Electronics has established a semiconductor packaging task force (TF). Supposed to work word-for-word under the CEO, which will enhance cooperation with customers in the packaging field for foundry business.
Samsung also announced in April this year that it will work on 2 nm by 2025. Before this, Samsung also informed in April that it would start to work on the 3nm chips 3GAE (3 nm-class gate-all-around early) fabrication process, starting in mid-2022, and it did.
Recently, The company’s DS Sales division, or TF has constituted in mid-June antecedently for this purpose. This team will report directly to DS Sales Division with CEO Kyung Kye-Hyun.
The Team & Its Goal:
- System Testing and Package (TSP) engineers from the DS division.
- Researchers from the R&D Semiconductor Center.
- Managers from the company’s memory division and foundry.
The goal would be to accomplish advanced packaging solutions to improve the cooperative relationship with customers.
Manufacturing, plans & Expectations:
The chipmaking tech is extremely difficult as to put a complex process that requires precision, clean environments, expensive factory equipment, and time. It takes GlobalFoundries three months on average to engrave and transform mirror-smooth silicon wafers into layered semiconductors and not to mention the lower the nm(nanometer) more difficult it becomes to fit the no. of transistors in a wafer-thin silicon layer.
So, a lower nm transistor means less power is required for it to work. When you look at all the transistors in a CPU, lower power consumption makes a huge difference overall. It makes your processor more power-efficient than a higher nm processor with larger transistors.
The CEO’s decision shows the importance of advanced semiconductor packaging technologies. The packaging procedure includes cutting a wafer that has met the end-to-end process in the form of a semiconductor or its wiring. Known as the “primary process” in this business.
Global semiconductor giants like Intel and TSMC are richly investing in cutting-edge packaging. Intel and TSMC account for 32% and 27% of total global investment in state-of-the-art packaging by 2022, respectively.
According to market research firm Yole Development data, Samsung Electronics ranks fourth after ASE, a Taiwanese outsourcing equipment manufacturing company.
Intel introduced a brand of 3D packaging called “Foveros” in 2018 and announced that it would apply the technology to various new products. It also devised a method of assembling each part of the product by turning it into a tile shape.
A chip called “Lakefield,” released in 2020, was made this way and installed in Samsung Electronics laptops.
TSMC also recently decided to manufacture the latest product from AMD, its biggest customer, using this technology. Intel and TSMC have been persistent sufficiently to establish a 3D packaging research center in Japan and operate it from June 2.
Meanwhile, Samsung will imply an advanced GAAFET (gate-all-around field-effect transistor) architecture compared to its archrival TSMC’s FinFET (fin field-effect transistor) fabrication method.
Samsung doesn’t want to lag and is working hard in this market by launching its 3D stacking technology, “X-Cube,” in 2020.
Choi Si-young, president of the Founding Business Division of Samsung Electronics, said they were developing a “3.5D packaging” at Hot Chips 2021 last June.
The recent CXL-based memory development by Samsung and collaborations with IBM, Intel, Montage Technology, AMD & others has already paved the way for Samsung in this regard.
This will conclude if this Samsung task force makes Samsung reduce the gap with its rivals in the field. Korean conglomerate’s technological advancement has given it an edge, and the current will it is showing to secure the leading position to its only rivals in this business, namely USA’s Intel & Taiwanese TSMC, could make its plan a success.
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